E-mail：HR@xinyisemi哥對.com
● Digital verification engineer
job requirements:
1. Bachelor's or 熱這master's degree in e紅東lectrical engineering, 2會兒-5 years of ASIC/SoC verifica技歌tion experience, skilled use of UVM
2. Proficient in AM紅視BA AHB/AXI/APB protocol, familiar w用水ith various common periph近術erals, such as I2C, UART, USB, etc.
3. Proficient in syste朋船m Verilog and various Shell langu商長ages (Perl, csh, tcl, sh,讀姐 etc)
4. Familiar with the 鄉爸design of HDL language道門, simulation tools and test pl明暗atform, assembly language and C or 商去C++, scripting language, etc.
5. Familiar with the microp冷都rocessor, DSP instruction set, and h制紅ow to integrate the driver so裡體ftware into the SoC system
6. Experience in RTL design/mo低公deling is preferred; experience in 雪房FPGA verification and chip verif麗金ication is preferred姐火
Job Responsibilities:
1. Develop various veri店老fication models and module-level ver喝姐ification components
2. Co-verification of MCU a光拿nd RTL, including application用媽 software and firmware
3. FPGA verification an銀校d chip testing
● RF analog engineer
job requirements:
1. Excellent undergradu用很ate master's degree
2. Solid analog RF circuit desig時線n basis
3. Designed the RF analog 討和circuit in the wireless transceiver用樂, with relevant tape ex醫近perience
description of job:
1. Design RF analog ci用通rcuit modules for various著通 wireless communication chi術美ps, including but not limited to the遠電 following modules: LNA, Mi樹作xer, PA, ADC, DAC, PMU
2. Complete or assist layout enginee你這rs to complete high quali是火ty layout design
3. Assist application e國睡ngineers to complete test ta近知sks for related modules
● Physical layer algori學我thm engineer
job requirements:
1. Graduated from an intern體日ationally renowned university in electr弟線ical engineering, with a doctor鄉低al degree
2. Proficient in digital communica離請tion and digital signal p新購rocessing
3. Familiar with modulation and demo年喝dulation algorithms, 慢很transmitter and receiver baseband wo喝跳rking principle
4. Have a good team spir事技it and be able to withst員道and the pressure of Silicon Valley sta錢學rtups
5. Priority: Experience w呢腦ith protocol standards such as LTE i爸地s a plus
description of job:
1. Physical layer baseband algo湖生rithm research and development
2.C and Matlab algorithm modeling a土工nd analysis, algorithm perf國刀ormance optimization on DSP
3. Track industry standards (3西冷GPP, IEEE, etc.) and participate 聽動in standard proposals
4. Track the developme計機nt of next-generation wireless短作 communications and in制熱formation processing technologies
● Digital verification enginee綠西r
job requirements:
1. Bachelor's or master北這's degree in elect中身rical engineering, 2-5 years of A用錯SIC/SoC verification ex場明perience, skilled use of UVM
2. Proficient in AMBA AH得做B/AXI/APB protocol, familiar with vari房小ous common peripherals,哥車 such as I2C, UART, USB, etc.體討
3. Proficient in system V有有erilog and various She雜拿ll languages (Perl, c麗鐘sh, tcl, sh, etc)
4. Familiar with the design of HDL制和 language, simulation tools an子地d test platform, assembly 得我language and C or C++, scripting lan場厭guage, etc.
5. Familiar with the microproce也藍ssor, DSP instruction set, and how鐘制 to integrate the driver 內明software into the SoC system
6. Experience in RTL design/modelin花外g is preferred; experience in F兵對PGA verification and chip verific東車ation is preferred
Job Responsibilities:兵相
1. Develop various verifi新土cation models and module-leve這習l verification components
2. Co-verification of MCU雪司 and RTL, including applicati做腦on software and firmware
3. FPGA verification妹購 and chip testing
● RF analog engineer
job requirements:
1. Excellent undergraduate master&好睡#39;s degree
2. Solid analog RF c裡城ircuit design basis
3. Designed the RF analog circui人男t in the wireless trans商人ceiver, with relevant tape experienc光個e
description of job:
1. Design RF analog circuit 林草modules for various w兵視ireless communication chips, includin高熱g but not limited to the following草東 modules: LNA, Mixer, PA, ADC, DA鐵們C, PMU
2. Complete or assist layout engineers音坐 to complete high quality layout 輛術design
3. Assist application engineers to co做放mplete test tasks for師線 related modules
